The subject matter disclosed herein relates to solutions for retargeting of integrated circuit layouts. More specifically, the subject matter disclosed herein relates to diffraction pattern optimization-based retargeting of integrated circuit layouts for improved printability.
As technology has advanced, devices and features on integrated circuits have shrunk to a size which may be extremely vulnerable to printing tolerances and clearances. Due to a lack of advanced lithographic technologies, printing of these features may be difficult as dimensions of these features may be a fraction of the wavelength of light which is being used for imaging. These limitations require that in the design and manufacture of integrated circuit devices, designers must account for attribute and dimensional variations which result from manufacturing processes (e.g., lithography, processing, etc.) and printability limitations. Devices and features which in the ideal/conceptual design are intended to have specific shapes, angles, widths, and borders, may, when actually manufactured on a chip, have variations in critical dimensions or electrical characteristics as a result of the limits of manufacturing processes and the relative positions of the devices and features on the chip. While the shape intended by the designer may meet the design rules for a given chip conceptually, the variations introduced by the printing process may lead to ‘hot spots’ (e.g., device overlap), poor performance, inefficiencies, and even failures.
Identifying and/or eliminating every troublesome construct during the design phase of the integrated circuit process, significantly increases the volume of design rules, and consequently the design overhead in terms of time and effort. Conventional approaches for limiting and/or anticipating and avoiding these manufacturing variations includes retargeting (e.g., modifying designer-drawn target shapes prior to preparing lithographic masks) of feature shapes. Some approaches for retargeting have included rule-based retargeting (e.g., a set of design rules which anticipate troublesome constructs), and/or mask and target optimization processes which simulate and adjust designs based on computer simulations. However, rule-based approaches cannot cover all possible two-dimensional layout configurations and hence fail to adequately account for all of the possible feature/device shapes. Further, simulation-based methods are computationally intensive, failing to efficiently and quickly produce a workable design.